Source ↗

A real processor,
on chain.

NO EMULATION · NAND BY NAND

2,368 NAND gates, 171 flip‑flops and 256 bytes of RAM, synthesised from Verilog. The contract does not emulate the processor—it walks every gate, every block, on Robinhood Chain. And every tick carries a byte from whoever paid it.

Run the processor → Read the datasheet
GATES2,368
FLIP‑FLOPS171
CLOCK1 BLOCK

LIVE · CHAIN 4663 · CHIP #1 LISTENING

RH‑8 / GATE ARRAY 2368 NAND · 171 FF · 256 B RAM LIVE / 00:00:00
CYCLE0
PC0x00
OUT0
FLAGS··
EVERY SQUARE IS ONE NAND GATE
EXECUTINGnop
01 GATES 1,029 NAND only. Inverters are NANDs with their inputs tied together.
02 FLIP‑FLOPS 79 Registers, PC, memory latches and flags — still one storage slot per tick.
03 GAS / CYCLE 256,740 Measured, not estimated. The price of a processor with input and memory.
04 RAM 256B Per chip, in storage. The processor asks, the contract answers — a load takes two honest cycles.

§ 02THE MACHINE

Watch it
think.

Not a recording. The netlist running above is the same one the contract interprets on‑chain: 2,368 NAND gates in topological order, then every flip‑flop latching at once — with its RAM and its input port handled here exactly as the contract handles them. Type a byte into the IN port and watch the program chew it.

CONTROL
CLOCK RATE
PROGRAM
IN PORT — YOUR BYTE
UPTIME @ 10 HZ 0.0 s
REGISTER FILE 16 × 4 BITS
PROGRAM / ROM 42 INSTRUCTIONS

§ 03THE FACTORY

Mint your own
processor.

Every chip is an NFT and a real processor, and it launches its own ERC‑20 with the name and ticker you pick. Fixed supply, no mint function, nothing to inflate. A slice goes to you for liquidity; all the rest leaves the factory one clock cycle at a time, to whoever paid that cycle.

DESIGN YOUR CHIP
LOGO
Click or drop an image
PNG, JPEG, GIF or WebP · up to 1 MB
optional — without one the NFT shows the live card
PAIR WITH
the market your chip trades against

Chip #1 is live and earning — browser minting is the first thing that ships after launch. The factory contract already accepts mints on‑chain.

YOUR CHIP, LIVE SVG BUILT ON‑CHAIN

No IPFS, no server. tokenURI builds this from the real 79 bits, so a stopped chip and a chip someone keeps alive do not look alike.

OPERATIONGASON ROBINHOOD CHAINNOTE
Deploy the whole stack~9,000,000~0.00024 ETHONCE PER CHAIN
Mint a chip + launch its token829,552~0.0000167 ETHROM, RAM AND TOKEN
One clock cycle256,740~0.0000052 ETHANYONE PAYS, ANYONE EARNS
WHY THIS HOLDS TOGETHER

A chip runs as fast as the market thinks it deserves.

Buying aside, the only way to get a chip’s token is to keep its processor alive. If the token is worth more than the gas of a tick, someone calls it and the chip keeps running. If it is not, the chip stalls — and that is the honest outcome. Emission is not governed by anyone: nobody can print faster than the chain closes blocks.

The shared gate array costs +1,301 gas per cycle over the standalone build — about 2%. Paying the sponsor adds ~6,900 more. That is the whole price of making chips cheap and their tokens earnable.

§ 04FABRICATION

From Verilog
to blockspace.

Nothing here is hand‑written assembly pretending to be hardware. The processor starts as Verilog and goes through a real synthesis toolchain.

  1. 01

    Verilog

    A 12‑bit instruction word, single‑cycle execution, our own ISA — not a clone of the 4004.

  2. 02

    yosys

    Synthesised to a single combinational primitive: abc -g NAND, then leftover inverters folded in too.

  3. 03

    Topological sort

    The EVM has no propagation, only a sequence. Gates must be ordered before they can be emitted.

  4. 04

    Yul codegen

    Each gate becomes one line: mstore(y, iszero(and(mload(a), mload(b)))).

  5. 05

    The chain

    tick() reads ROM[pc], evaluates the cone, latches the flops, writes one slot.

VERIFICATION

Three simulations have to agree, cycle for cycle.

RTL simulation, gate‑level simulation of the synthesised netlist, and execution inside the EVM. The Solidity test suite does not check the contract against itself — it checks that the contract behaves like the hardware.

§ 05INSTRUCTION SET

Twenty‑nine
opcodes.

12‑bit words. Sixteen registers of four bits, an 8‑bit program counter, 256 words of ROM. Every instruction completes in one block.

OPMNEMONICEFFECTFLAGS
0nop—
1ldi rd, #immrd ← imm8
2mov rd, rsrd ← rs
3add rd, rsrd ← rd + rsC Z
4adc rd, rsrd ← rd + rs + CC Z
5sub rd, rsrd ← rd − rsC Z
6sbb rd, rsrd ← rd − rs − CC Z
7and rd, rsrd ← rd & rsC Z
8or rd, rsrd ← rd | rsC Z
9xor rd, rsrd ← rd ^ rsC Z
10nand rd, rsrd ← ~(rd & rs)C Z
11not rdrd ← ~rdC Z
12shl rdrd ← rd << 1C Z
13shr rdrd ← rd >> 1C Z
14rol rdrotate left through CC Z
15ror rdrotate right through CC Z
16inc rdrd ← rd + 1C Z
17dec rdrd ← rd − 1C Z
18cmp rd, rsflags of rd − rs onlyC Z
19ld rd, [rs]rd ← RAM[rs] — two cycles
20st [rd], rsRAM[rd] ← rs
21in rdrd ← the byte from tick()
22out rdoutput port ← rd
23jmp addrpc ← addr
24jz addrif Z
25jnz addrif ¬Z
26jc addrif C
27jnc addrif ¬C
28hltstop the processor

There is a nand in the instruction set because the processor is NANDs. It seemed rude not to.

§ 06THE CLOCK

Nobody owns
the clock.

tick() is open to anyone, once per block. Whoever calls it pays the gas for that cycle and is written into the Cycle event as its sponsor. No privileged keeper, no scheduler — the processor advances because someone wanted it to.

THE PROGRAM CANNOT STOP

The program running on it has no hlt, and cannot have one. If the RH‑4 ever halts it halts forever, so the loop is checked over 20,000 cycles against the synthesised netlist and 5,300 cycles inside the EVM before anything is deployed.

POWER A CHIP ROBINHOOD CHAIN

One tick, one block, one cycle. Whoever sends it pays the gas and earns that cycle’s share of the chip’s token.

The byte rides along with your tick — it is what the program reads with IN.

not deployed yet — the button opens at launch

or from the command line 
cast send $FACTORY "tick(uint256,uint8)" 1 165 \
  --rpc-url https://rpc.mainnet.chain.robinhood.com \
  --private-key $PRIVATE_KEY
DEPLOYMENT
Status
LIVE
Network
ROBINHOOD CHAIN / 4663
Mother chip
#1 — RH4 CPU (RH4) · running echo8
Clock rate
10 HZ / 100 MS BLOCKS

§ 07THE POINT

Not faster silicon.
Provable silicon.

A blockchain cannot replace physical chips — it runs on physical chips. Every cycle the RH‑8 executes is re‑executed by every validator on the network: on‑chain compute is not an alternative to silicon, it is silicon times redundancy. Anyone promising to replace GPUs with a chain is selling physics that does not exist. What the chain has, and the datacenter never will, is a different property entirely.

THE PROPERTY

A physical chip cannot prove what it did. This one can.

An AI answers, a computation returns a number — and you take someone’s word for it. Verifiability is the one thing the chain adds to silicon: every cycle here is public, deterministic, and re‑executable by anyone, forever. The question is never how fast it computed — it is whether anyone can check that it did.

  1. NOW

    A live processor

    Every cycle paid for, signed and engraved. A machine whose entire history — every byte it was ever fed — is auditable down to the gate.

  2. NEXT

    Compose and batch

    Many cycles per transaction, chips wired into chips, and a neural network synthesised to NAND — inference running gate‑level inside the chain.

  3. GOAL

    The verifiable co‑processor

    The processor runs off‑chain at full speed. The result is posted with a bond. A dispute bisects to the single contested cycle and replays it inside the gate array — the chain stops being the engine and becomes the court.

The hard primitive of that court — a pure, deterministic step() that executes exactly one cycle — is not a roadmap item. It is built, and verified against the silicon on four independent layers: RTL simulation, the synthesised netlist, the interpreter alone, and a minted chip.

§ 08ROADMAP

What ships,
in order.

Nothing here is a maybe. Each release is either pure software around contracts that never change, or a new generation of silicon that must pass the same four proofs the current one did. The project token carries through all of it — it never relaunches.

  1. R1

    The launchpad opens

    Minting from the browser: pick a program, upload a logo, choose what your chip trades against — ETH or tokenised stocks (NVDA, SNDK, SPCX). No contract changes; the factory already accepts every mint.

  2. R2

    The court

    The first protocol upgrade. Processors run off‑chain at full speed; results post with a bond; a dispute bisects to one cycle and replays it inside the deployed gate array. Off‑chain speed, on‑chain truth — and the hard primitive is already live.

  3. R3

    Wider silicon

    RH‑16, then RH‑32, then RH‑64 — from the home‑computer class to a real RISC core — plus RAM up to 64 KB and many cycles per transaction. Each generation is new silicon beside the old, never a rug under it: same token, four proofs, every time.

  4. R4

    Silicon for AI

    A neural network synthesised to NAND — inference running gate‑level inside the chain — and AI agents as sponsors, paying ticks and feeding bytes to chips of their own.

THE GOAL THAT MATTERS MOST

Virtual silicon in service of AI.

Not by replacing GPUs — physics does not allow it and we will never claim it. By giving AI the one property physical chips cannot offer: the ability to prove what was computed. An AI whose inference runs through the court can show its work — every cycle public, deterministic, re‑executable by anyone. That is what these chips are for: not faster answers, answers you can check.

§ 09THE DESIGN

Ours,
end to end.

RH‑4 is an independent design with its own ISA, its own netlist and its own toolchain, built for a chain whose blocks close in 100 ms.

WHY THE 4

The 4 does not count bits. It counts proofs.

The project was born as a 4‑bit processor, and the name stayed the way a 911 keeps its number. But the 4 stopped counting bits almost immediately: it counts the four independent layers of verification every generation of silicon must pass before it breathes on mainnet — RTL simulation, the synthesised netlist, the interpreter alone, and a minted chip, all required to agree cycle for cycle. The bits will grow with each generation. The proofs stay four.